**Solving Circuits, the easy way**

Before we dive into the nitty-gritty of circuit solving, let’s first build up a good foundation to tackle these problems head-on. You’ll be a circuit-solving master in no time…heck, I’ll probably be coming to you for any circuit problems that I have in the future. So let’s buckle up and learn some important concepts.

Concept numero uno, that’s number one in Spanish. See, Spanish lessons and circuit-solving skills, what a good

*bang for your buck*lesson, although this lesson is absolutely free… wow I feel cheated already :)**Concept #1: Kirchhoff’s Current Law**

This Law is the most important to grasp, as it will provide you with valuable insight into future circuits. Kirchhoff’s Current Law, or KCL for short, states that the sum of currents flowing into a node must be equivalent to the sum of currents flowing out of the node. This should intuitively make sense since flowing charge can either enter a node or exit a node, as charge cannot build up at a node. In electronics, moving charge is represented as ‘current’, also known as ‘I’.

**Figure 1**. KCL Equations for current Entering and Exiting a Node

A good analogy to use is that of a flowing river. In this case, the water in a river can be represented as ‘charge’. Water flowing in any spatial direction can also be represented as a current. Therefore, let’s suggest that two flowing rivers combine into one river, as Figure 2 illustrates. The point at which both rivers merge into one can be labeled as a node. The water of the two rivers entering the node must be equivalent to the amount of water exiting the node.

**Figure 2**. River representation of KCL

A mathematical expression of
this law is provided below. The main
takeaway is that the algebraic sum of all currents entering and exiting a node
equate to zero.

*n*= number of branches with currents entering or exiting the node

**Concept #2: Kirchhoff’s Voltage Law**

This
Law states that all voltage drops across all circuit elements within a loop of
a network must equate to zero. When
adding voltages ensure that you proceed in one direction around the loop,
either clock-wise or counter-clockwise.
A simple visual representation of this concept is provided in Figure 3.

**Figure 3**. KVL (a) Clockwise loops (b) Counter-Clockwise loops

A mathematical expression of this law can be seen as:

Again the main concept is that the algebraic sum of all potential drops
within a loop of a network is zero.

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